Multistep analog-to-digital converter with successive approximation register circuit for least significant bit resolution
US5287108A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1992 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Jul 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a "parallel successive approximation register" circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value. A set of successive comparison voltages are generated in the third conversion cycle by selectively switching combinations of reference voltages with binary weighted capacitors. The resulting comparison voltages are stepped in 1 LSB increments, which is one fourth the voltage increment between neighboring ref…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.