Timing recovery for variable bit-rate video on asynchronous transfer mode (ATM) networks
US5287182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1992 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Jul 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5646
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Complications of timing recovery in an ATM receiver are overcome by employing a first phase lock loop including a phase comparator, filter, voltage controlled oscillator (VCO) and output counter to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then, so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data. Invention, underflow of the receiver data buffers is alleviated by the addition of a "jitter-delay (D.sub.j)" value which causes an extra accumulation of data in the data buffers prior to decoding. Dynamic tracking of the jitter-delay of the channel is obtained by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly. The s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.