Synchronous decoder for self-clocking signals
US5287359A · kind A · utility
11Cited by
17References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1991 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Apr 8, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for receiving and decoding Manchester-encoded communication signals such as those used in an Ethernet network. The circuit uses a single local reference clock signal to clock a shift register that temporarily stores samples of the incoming signal. A window pointer selects a particular bit of the shift register as the current output bit; the value of the window pointer is maintained by a feedback loop which tracks any phase error in the incoming signal, that the output data remains in phase with the incoming signal. The combined functions of a Manchester-decoder and retiming circuit are thus provided in a simple circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.