Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transitions
US5287463A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1990 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Jul 19, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An atomic ordered sequence of information phase transitions allows for the design of a pure hardware protocol controller for use in a small storage interconnect bus. The information phase transitions follow the sequence: Command Out phase, Data Out phase, and Status In phase. The only other transition sequence allowed is from the Command Out phase directly to the Status In phase. The Command Out phase is actually a header delivering header information. Included in the header are a REQ/ACK offset byte, source destination ID verify byte, frame length bytes, and a checksum byte. The Data Out phase contains any number of bytes that were defined in the Command Out frame length byte. The Status In phase is a single byte which is used to signal the outcome of the attempted data delivery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.