Predictive caching method and apparatus for generating a predicted address for a frame buffer
US5287487A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1993 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Jun 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A predictive caching system for use in computer system having at least one portion of memory in which information is stored for retrieval, a general cache used to speed the operation of accessing such memory, and a processor for controlling the access of the memory comprising apparatus for discerning a pattern of access of the memory, apparatus operating in response to the pattern determined by the apparatus for discerning a pattern of access of the memory for determining a next address which will probably accessed in such memory if the pattern discerned continues, and apparatus for storing the information at the next address determined prior to the next access of the memory whereby the information at the next address is available without the need to access the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.