System having control registers coupled to a bus whereby addresses on the bus select a control register and a function to be performed on the control register
US5287503A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1991 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | Sep 27, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/521
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer storage register architecture permitting secure atomic access to set or clear one or more particular bits wherein a multiple bit register is disclosed. In the preferred embodiment, a multiplicity of unique addresses is assigned to a multiple bit register. One address constitutes a read address, one address constitutes a clear address, and a third address constitutes a set address. An address decoder decodes the addresses assigned to the register so that only that register is accessed for the associated read, clear, and set operations, respectively. Data having a register position equivalent binary pattern of logical zeros and ones corresponding to particular bit locations of the register to be set or cleared are associated with the set and clear addresses. If the position equivalent binary value of the data associated with the address decoded is a logical one, then the corresponding bit in the register will be set or cleared. Otherwise, the bit remains unchanged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.