Compensating lead structure for distributed IC components
US5289040A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1991 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Aug 12, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/919
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit constructed using exposure and etching steps in an FET fabrication process incorporates electrical lead structures coupled to distributed IC components to compensate for process variation. The electrical lead structure (10,14,16,24,34is composed of an etchable conductive layer constructed in a configuration with graduated coupling widths (B,C,D,E . . . ) forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence. A primary lead (IA) is coupled at a first end to the widest coupling width (B). A plurality of secondary leads (0B,0C,0D,0E . . . ) distributed along the electrically coupled sequence of graduated coupling widths are coupled respectively to the distributed electrical component elements (P1B,P1C,P1D,P1E . . . ) (N1B,N1C,N1D,N1E . . . ) (RB,RC,RD,RE . . . ) of a distributed electrical component such as a PMOS transistor (P1) NMOS transistor (N1) or resistor (R). The graduated coupling widths (B,C,D,E . . . ) of the electrical lead structure (10,14,16,24,34) electrically couple the secondary leads (0B,0 C,0D,0E . . . ) to the primary lead (IA) through incremental portions of the electrically coupled sequence …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.