Multi-master resolution of a serial bus
US5289176A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1992 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Mar 19, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for determining an overall master node for an overall communication network with a serial bus, wherein the overall communication network comprises an original communication network connected to a new communication network via a serial bus with high level data link control (HDLC) packets. The method and apparatus are especially applicable to trainline monitor systems since such systems are frequently divided up and rearranged because their associated trains are frequently divided up and rearranged. The method involves performing a series of steps in order to relinquish mastership of certain master nodes placing those master nodes in an inactive state and making a desired master node an overall master node of the resulting overall trainline monitor system, and the apparatus involves a corresponding series of means for performing these steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.