Sense amplifier and latching circuit for an SRAM
US5289415A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1992 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Apr 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit uses sense amplifiers to amplify a low level differential data signal from the memory cells to full logic levels. A first sense amplifier converts the low level differential data signal to an intermediate differential voltage level at first and second nodes during the read cycle. A second sense amplifier converts the intermediate differential voltage level to the full logic level. The first and second sense amplifiers are powered down after sensing is complete. A circuit drives the intermediate differential data signal to an equilibrium voltage level when the sensing is complete to reduce the power up delay time of the second sense amplifier and thereby increase the operating speed of the memory circuit. A latching circuit is synchronized with the power down of the first sense amplifier to latch the output logic level at the end of the read cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.