Memory apparatus with built-in parity generation
US5289418A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1992 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Feb 14, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a dedicated memory circuit which supports the generation of parity data in connection with the storing of data. This improved memory circuit allows the parity generation to be done remotely from the CPU while consuming less time. The memory array is provided with its data output being connected to combinational logic. Another input to combinational logic is for external data. The data already in the array and the new data are combined to the combinational logic, preferably an exclusive-or arrangement, to produce the parity data which is then returned to the memory array. A latch is provided between the exclusive-or logic and the memory array data lines to allow isolation of the data during the two cycles of the read out of the array and the right back to the array after the exclusive-or.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.