Multiport memory with write priority detector
US5289427A · kind A · utility
15Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1992 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Jul 20, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write priority detector in a multiport memory prioritizes write operations to memory cell by activating one of its enable signals to a memory cell upon receiving multiple address signals at different write ports of the multiport memory, each attempting to access the same memory cell. The other enable signals are de-activated. One prioritization scheme provides first-come first-serve access to the memory cell among completing address signals. Alternately, a fixed priority scheme always gives one enable signal first priority.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.