Process-pipeline architecture for image/video processing
US5289577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1992 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Jun 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A sequential process-pipeline (12) has a first processing stage (30) coupled to a CODEC (24) through a plurality of buffers, including an image data input buffer (28), an image data output buffer (26), and an address buffer (34). The address buffer stores addresses, each of which identifies an initial address of a block of addresses within an image memory (22). Each block of addresses in the image memory stores a block of decompressed image data. A local controller (18) is responsive to the writing of an address into the address buffer to initiate the operation of the CODEC to execute a Discrete Cosine Transformation Process and a Discrete Cosine Transformation Quantization Process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.