Simplified high reliability gate oxide process

US5290718A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Paul A. Fearon · Gorham, US
• Todd Thibeault · Brooks Road, US

Key dates

• Filing date: Jun 29, 1992
• Grant date: Mar 1, 1994
• Expiry date: Jun 29, 2012

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/082
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A new IC wafer fabrication process provides an improved CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence particularly applicable for preparation of CMOS transistors in BICMOS wafers. The new gate oxide process reduces the number of process steps and thermal cycles, increases the reliability of the gate oxide layer, and substantially reduces differential stress and thermal stress related structural silicon defects in the epitaxial silicon. The process proceeds by forming a photoresist CMOS active strip mask exposing CMOS transistor active areas, etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer. Further steps include introducing dopant material through the EPIOX layer into the EPI layer of CMOS transistor active areas with the photoresist active strip mask in place and adjusting the threshold voltage V.sub.T of the CMOS transistors. The invention proceeds by stripping the EPIOX layer over the CMOS transistor active areas without growing a sacrificial oxide SACOX layer, and then removing the photoresist CMOS active strip mask. This step is followed by growing a gate oxide layer over the CMOS transis…