CMOS semiconductor device with (LDD) NMOS and single drain PMOS
US5291052A · kind A · utility
32Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1991 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Aug 30, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
A MOS semiconductor device and the methods for constructing the device. The MOS device provided with first and second MOS transistors are formed on two identical wafer sections. The impurity region of the first transistor and a first group of gate side wall spacers are aligned to the gate of the first transistor. The impurity region of the second transistor and a second group of gate side wall spacers are aligned to the gate of the second MOS transistor. The second group of gate side wall spacers have a thickness different from that of the first group of gate side wall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.