Multi-bit encoder signal conditioning circuit having common mode disturbance compensation
US5291133A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1992 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Aug 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01P3/489
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A signal conditioning circuit which converts multiple analog signals received from an encoder into a multi-bit digital signal, corresponding to the angular position of a rotary object, which is independent of any common mode disturbances such as temperature, humidity, ambient light and aging. At any given time, at least one of the analog signals is at a maximum voltage and at least one of the analog signals is at a minimum voltage. At no time are all of the analog signals simultaneously at a maximum or simultaneously at a minimum. The signal conditioning circuit continuously detects the maximum and minimum values of the analog signals. A midpoint of the maximum and minimum values is determined and compared with the original analog signals. For all values of the analog signals greater than the midpoint value, a binary logic level of 1 is outputted. For all values of the analog signals less than the midpoint value, a binary logic level of 0 is outputted. There is one comparator and corresponding binary output for each analog signal. In combination, the comparators form the necessary multi-bit digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.