Averaging flash analog-to-digital converter
US5291198A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 29, 1992 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | May 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks. In other embodiments of the invention the ADC is implemented in CMOS technology and the pseudocomparators use ratioed transistor widths and ratioed capacitors to proportionally divide the output signals of the actual comparators in order to generate the inte…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.