Shared dummy cell
US5291437A · kind A · utility
18Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 1992 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Jun 25, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4099
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention describes a circuit and method for utilizing a single dummy cell for each sense amplifier in a dynamic random access memory (DRAM) device. A precharge transistor connects a dummy cell capacitor to a reference potential and decoded selection transistors. The use of decoded selection transistors provides a means to share the dummy cell capacitor between either input of a differential or sense amplifier thereby reducing required area and circuit complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.