Electrically programmable read only memory device with timing detector for increasing address decoding signal
US5291441A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1991 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Aug 27, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable read only memory device in a read-out mode of operation lifts one of the word lines to a read-out voltage level higher than an external power voltage level to see whether or not a designated floating gate type memory transistor provides a conductive channel, and the selected word line is firstly lifted to a first predetermined voltage level with a power voltage line, then being further lifted to the read-out voltage level supplied from a step-up circuit, wherein a monitoring unit is provided for the word lines for detecting the first predetermined voltage level so that an address set-up period is minimized without margin for fluctuation of process parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.