High bandwidth packet switch
US5291482A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 1992 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Jul 24, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3027
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A fast packet switch comprising one buffer directly connected between a plurality of input ports and a plurality of output ports to effect rapid throughput of data packets. A pointer to a location in the buffer is allocated by a buffer manager upon receipt of notification of an incoming packet at the receiving input port and the input port delivers the packet as it is received to the location designated by the pointer. After the data packet is received, the input port delivers the pointer and a destination address for the packet to a router, which selects one of the plurality of output ports based on the destination address. The router queues the pointer in a queue for the selected output port. The output port then retrieves the data packet from the buffer using the pointer to determine the location, and transmits the data packet. After the transmission is complete, the output port returns the pointer to the buffer manager. This packet switch may be pipelined to receive, route, and transmit simultaneously on adjacent data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.