Interprocessor switching network
US5291489A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1992 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Feb 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5627
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths. The message transport network (10) may be used in variety of applications, such as a telephony switch (11), a signaling transfer point system (21) or a fault tolerant minicomputer (49).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.