Error detecting method and apparatus for computer memory having multi-bit output memory circuits
US5291498A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1991 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Jan 29, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single bit errors and detecting the existence of multi-bit errors. A parity bit for the entire data word is also stored. For a 32-bit data word, at least 3 bits of the data word are stored in each of 10 memory circuits. Seven check bits and one parity bit are also stored in the 10 memory circuits wherein no more than one of the check bits or parity bit is stored in any one memory circuit. Upon reading the data word from the memory a set of verify check bits and a verify parity bit are generated and compared to the stored check bits and stored parity bit to produce a check bit syndrome and a parity bit syndrome. The check bit syndrome is decoded to produce an output that is input to an error generator circuit together with a parity syndrome for producing error signals indicating occurrence of a single bit error, a multi-bit error, a triple bit error, or a check bit error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.