FET nonvolatile memory with composite gate insulating layer
US5293062A · kind A · utility
3Cited by
0References
4Claims
0Family size
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Key dates
| Filing date | Dec 2, 1991 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Dec 2, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.