Pattern layout of power source lines in semiconductor memory device
US5293334A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 1991 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Nov 27, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first power source line is formed around a memory area having a memory cell array, column decoder, row decoder and sense amplifier formed therein. The first power source line is applied with a potential which is obtained by lowering a power source voltage supplied from the exterior. A second power source line is formed in the surrounding region of the first power source line. The second power source line is applied with a ground potential. A first peripheral circuit driven by a voltage between the lowered potential and the ground potential is disposed in an area between the first and second power source lines. The first peripheral circuit is a circuit used for the memory area. A third power source line is formed in the surrounding region of the second power source line. The third power source line is applied with a power source potential supplied from the exterior. A second peripheral circuit driven by a voltage between the power source potential and the ground potential is disposed in an area between the second and third power source lines. The second peripheral circuit is a circuit used for an external circuit of a chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.