Dynamic semiconductor memory having a read amplifier drive circuit for achieving short access times with a low total peak current

US5293343A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Wolfgang Raab · Hersbruck, DE
• Heribert Geib · Grafing, DE

Key dates

• Filing date: Mar 10, 1993
• Grant date: Mar 8, 1994
• Expiry date: Mar 10, 2013

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4097
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The dynamic semiconductor memory is divided into word line blocks and bit line blocks, word line blocks consisting of a plurality of bit line blocks, which includes for each bit line block a local SAN driver (LTN) and an decelerator circuit for driving the read amplifiers (LV1 . . . LVi) associated with the respective bit line block, and the accelerator circuits of which can be driven in such a way that, to achieve a low total peak current, only the accelerator circuit belonging to the bit line block is active whose bit lines are switched through to IO lines (IO, ION). The accelerator circuit consists, for example, of only one driver transistor (NT.sub.n+1) in each case.