Compression/decompress with ECC data flow architecture
US5293388A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1990 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Nov 13, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1833
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An architecture for providing hardware compression/decompression with ECC to data flow in a computer system utilizes a hardware implementation of the compression/decompression circuit in a peripheral adapter of one of many peripheral devices. Error correction coding is provided by software in the host RAM. The compression/decompression circuit can be located in the periphery and can service a number of peripheral devices. The CPU and DMA controller in the host computer are capable of providing concurrent processing for hard disk operation, peripheral control (such as a tape or a modem), compression/decompression of data, and error correction coding of the compressed data. This significantly speeds up the performance of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.