Preemption control for central processor with cache
US5293493A · kind A · utility
8Cited by
16References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1989 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Oct 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic controlled gate is inserted in the arbitration logic of a computer system that supports multiple masters on a data bus. In such a system with arbitration for data bus ownership, the gate is so controlled that competitors for the data bus cannot force the main processor (CPU) from the data bus until certain system conditions are met. In particular, a pattern of CPU "hits" to memory cache is recognized as an opportunity for the CPU to relinquish the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.