Apparatus for executing a RISC store and RI instruction pair in two clock cycles
US5293499A · kind A · utility
11Cited by
13References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1990 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Sep 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for a SPARC based RISC computer including a central processing unit including a register file having a pair of read ports and a write port, an instruction register for holding an instruction including addresses of registers to be read and written to, a multiplexor, and apparatus for controlling the multiplexor to transfer the address from a write position of the instruction register to the register file such that the information stored in the addressed register is transferred out of the register file through one of the read ports on the clock cycle following a store instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.