Decoder for pipelined system having portion indicating type of address generation and other portion controlling address generation within pipeline
US5293592A · kind A · utility
40Cited by
10References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1993 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | May 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved instruction decoder is described which uses parallel stages which operate in a pipeline fashion. The decoder is particularly useful in a microprocessor which has variable length instructions. The first stage decodes the OP code and register and address mode specifier fields while the second stage directs the sequencing of address calculations. The first two lines of microcode are provided by the first stage as well as a look up to microcode in the microcode memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.