Data processing system having a plurality of register groups and a logical or circuit for addressing one register of one of the register groups
US5293594A · kind A · utility
9Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1990 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Apr 3, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage efficiently these memory areas, the address to be accessed inside the memory is determined on a software basis by a computer instruction by use of the value of a first pointer designating each memory area and the value of a second pointer designating the relative address in the designated memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.