Apparatus to supplement cache controller functionality in a memory store and a cache memory
US5293605A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1991 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Mar 4, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer comprises a CPU (11), a memory store (12) and a cache comprising a cache memory (17) and a cache controller (16), the CPU (11) being capable of receiving from a memory store (12), or from the cache memory (17), elements of data each arranged as a plurality of words of data associated with a common address, the cache controller (16) inherently only being capable of handling elements of data arranged as a single word of data and an associated address, there being provided a state machine to enable the cache controller (16) to handle elements of data each arranged as a plurality of words of data associated with a common address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.