System and method for optimizing cache memory utilization by selectively inhibiting loading of data
US5293608A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1991 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Apr 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for optimizing the utilization of a cache memory in an input/output controller in a computer system which also includes a central processing unit and a plurality of direct access storage devices. The optimizing system calculates a demotion time where the demotion time is an approximation of the length of time that a track of data will reside in the cache memory in the input/output controller after its last input/output request from the central processing unit. The optimizing system further intercepts an input/output request from the central processing unit for a requested track of data, determines an elapsed time between successive input/output requests from the central processing unit for the requested track of data, determines whether the elapsed time is greater than the demotion time and optimizes the requested track of data by inhibiting the requested track of data from being loaded into the cache memory if the elapsed time is greater than the demotion time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.