Clock distribution apparatus and processes particularly useful in multiprocessor systems
US5293626A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1990 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Jun 8, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement of optical elements physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.