Single-transistor cell EEPROM array for analog or digital storage
US5294819A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1992 |
| Grant date | Mar 15, 1994 |
| Priority date | — |
| Expiry date | Nov 25, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array. Array operating voltages are chosen such that "program disturbance" is eliminated on cells adjacent to a cell undergoing programming. Finally, the present invention utilizes only a single polarity of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.