Efficient method for multichip module interconnect
US5295082A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1991 |
| Grant date | Mar 15, 1994 |
| Priority date | — |
| Expiry date | May 30, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49171
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for interconnecting integrated circuits (ICs) mounted on a multichip module so as to minimize spacing between the ICs and maximize their density. A multichip module (20,80) includes a plurality of ICs (22,82) that are mounted on a substrate (24,84). The ICs are electrically connected to pads (28), spaced apart from each other and offset from the boundaries of the ICs to define vertical routing channels (35) and horizontal routing channels (42). The horizontal routing channel includes a top routing channel (36), a bottom routing channel (38), and a central routing channel (40). Initially, a minimal number of tracks are provided in the central routing channel. Each pad has an electrical connection point or pin (44,46) associated with it and the pins are organized into nets. The method provides for dividing the nets into two pin subnets. Each subnet in the horizontal routing channel is assigned to a vertical track so as to minimize violation of a constraint graph. Horizontal tracks are assigned to the subnets so as to minimize an associated element in a COST matrix of subnets and tracks. The method uses a conventional maze router approach to connect pins in subnets not otherw…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.