Arrangement for monitoring the bit rate in ATM networks
US5295135A · kind A · utility
34Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1992 |
| Grant date | Mar 15, 1994 |
| Priority date | — |
| Expiry date | Aug 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5637
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
For dual leaky bucket ATM bit rate monitoring, a peak bit rate is monitored in a first leaky bucket unit and a maximum cell plurality of a full rate burst is defined. A duration of peak rate bursts is monitored in a second leaky bucket unit with a first counter respectively reset to 0 when the counter reading returns below a defined value. An average bit rate is monitored with a further counter having a lower response value that is incremented with a cell rate which is smoothed dependent on a degree of filling in an additional cell counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.