Bidirectional FIFO buffer for interfacing between two buses of a multitasking system
US5295246A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1993 |
| Grant date | Mar 15, 1994 |
| Priority date | — |
| Expiry date | Jul 13, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached. A buffer counter indicating the amount of data in each FIFO is initialized at zero for outbound transfers from the workstation to the adapter or at the maximum buffer count for inbound transfers from the adapter to the workstation. The buffer count is incremented in response to accesses from the workstation side and is decremented in response to accesses from the adapt…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.