Fault-tolerant computer system with online recovery and reintegration of redundant components
US5295258A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1990 |
| Grant date | Mar 15, 1994 |
| Priority date | — |
| Expiry date | Jan 5, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2736
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.