Clock distribution system
US5296748A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1992 |
| Grant date | Mar 22, 1994 |
| Priority date | — |
| Expiry date | Jun 24, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/1445
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A seamless clock distribution scheme for a system incorporating sequential digital logic devices disposed on multiple parallel boards for reducing or substantially eliminating skew. The multiple parallel boards are positioned on and project outward from one side of a centerplane. A single clock board, generating multiple copies of the system clock and mounted at a right angle to the parallel boards on the opposite side of the centerplane are connected by shared pins passing through apertures formed in the centerplane. This shared pin connection allows for simple, though near-ideal transmission of the clock signal copies between the parallel logic boards and the clock board with a minimum mismatch of the clock signal between two parallel boards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.