Method and apparatus for deferred package assignment for components of an electronic circuit for a printed circuit board
US5297053A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1991 |
| Grant date | Mar 22, 1994 |
| Priority date | — |
| Expiry date | Jun 4, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer aided design tool provides a user with the capability of generating a design implementation for electronic circuitry. In this system the user generates a design schematic specifying a functional description of a design for electronic circuitry without the need for specifying packaging information. The system is provided with a packaging tool for generating a physical package for the circuitry of the design schematic. Use of the packaging tool may be deferred until the design schematic has been completed and verified. Further, a user of the system has the option of specifying certain packaging information when creating the design schematic or delaying such specification until just prior to packaging of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.