Method and apparatus for clock recovery for digitally implemented modem
US5297172A · kind A · utility
11Cited by
15References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1991 |
| Grant date | Mar 22, 1994 |
| Priority date | — |
| Expiry date | Apr 11, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The correct sampling timing phase is obtained by a digital data receiver by averaging samples of the preamble of a received data burst and using the computed averages as addresses to a memory which stores correction values for the timing phase. The output of the memory is sent to a phase correction circuit for correcting the phase of the presently received data burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.