Apparatus and method for synchronizing a digital data clock in a receiver with a digital data clock in a transmitter
US5297869A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1992 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Mar 26, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiving apparatus for synchronising a digital data clock in a receiver with a digital data clock in a transmitter and a method therefor is disclosed which utilizes two phase-locked loops so as to improve accuracy and jitter performance. One of the phase-locked loops is locked onto positive edges in a received waveform and the other phase-locked loop is locked onto negative edges. The phase-locked loops independently decode the 1's and 0's in the data allowing the transmit data and clock to be readily recovered. Each of the phase-locked loops uses a decoding method in which mid-bit transitions in the encoded received waveform are detected in more than half of the sampling periods within one bit period which further improves the performance of the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.