Gate array system semiconductor integrated circuit device
US5298774A · kind A · utility
113Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1992 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Mar 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
Abstract
Disclosed is a semiconductor integrated circuit device of a gate array system making it possible to mount a digital circuit and a high-precision analog circuit on a common substrate. This semiconductor integrated circuit device includes a basic cell array formed by a plurality of NMOS transistors and a plurality of PMOS transistors formed in rows on a semiconductor substrate. The basic cell array includes a plurality of N well regions formed in rows on the semiconductor substrate, P well regions and well terminal regions. The P well regions or N well regions are divided into small regions of the other conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.