Clock distribution circuit with active de-skewing
US5298866A · kind A · utility
Inventor
Key dates
| Filing date | Jun 4, 1992 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Jun 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock distribution circuit with multiple clock drivers distributing a clock signal on multiple signal paths has active de-skewing logic circuitry for equalizing the total clock delay to the different clock recipient circuits in a system. The de-skewing logic uses a return path parallel to the outward signal path to sense the propagation delay and includes a phase comparator with inputs receiving the return signal and a reference signal for comparison of their phase. Voltage-controlled delay elements, responsive to a control voltage provided by a charge pump controlled by the phase comparator, adds or removes equal amounts of delay to the outward and return signal paths until the return signal phase matches that of the reference signal. Each clock driver may have its own de-skewing circuitry or may share a common reference signal. In one embodiment the de-skewing circuitry for each driver time-shares a common phase comparator and charge pump, using sample-and-hold circuits to store the control voltages obtained by the comparisons. Input receivers on the return paths may have selectable input buffers to take into account the different buffer delays of different logic family types o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.