Method and device for improving performance of a parallel write test of a semiconductor memory device
US5299161A · kind A · utility
16Cited by
11References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1991 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Nov 18, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having normal columns and redundant columns includes normal column decoders for designating the normal columns and redundant column decoders for designating the redundant columns so that the bits from the normal columns are combined with the bits from the redundant columns so as to provide an entire byte. The normal column decoders are to be operated simultaneously with the redundant column decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.