Semiconductor memory having one-transistor/one-capacitor memory cells and having both improved noise ratio and high density integration
US5299165A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1991 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Oct 11, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory, a dummy data line having dummy cells connected thereto for producing reference signals is provided in common to a plurality of data lines having memory cells connected thereto. The dummy cells and the memory cells are selected by a same word line. Each of the data lines and the dummy data line are provided with signal transfer circuitries. A differential signal detecting circuit provided for each of the lines is supplied as input thereto with an output of the signal transfer circuit together with an output of the signal transfer circuit of the dummy data line for signal detection. By connecting the dummy cell to the dummy data line provided in common to the word line to which a same signal as that for the memory cell is applied, noise transmitted to the data line and the dummy data line can be canceled out. High density integration comparable to that of an open data line arrangement and a high S/N ratio comparable to that of a folded data line arrangement can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.