High performance interlock collapsing SCISM ALU apparatus
US5299319A · kind A · utility
27Cited by
11References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1991 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Mar 29, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4991
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Three high performance implementations for an interlock collapsing ALU are presented as alternative embodiments. The critical path delay of each embodiment provides reduction in delay. For one of the implementations the delay is shown to be an equivalent number of stages as required by a three-to-one adder assuming a commonly available bookset. The delay for the other two implementations is comparable to the three-to-one adder. In addition, trade-offs for the design complexity of implementation alternatives are set out. The embodiments achieve minimum delays without a prohibitive increase in hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.