Voltage interfacing buffer with isolation transistors used for overvoltage protection
US5300832A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 10, 1992 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Nov 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage interfacing buffer for interfacing a low voltage integrated circuit to a high voltage environment, wherein the integrated circuit contains only low voltage transistors. To drive the high voltage environment at the low voltage swing, the voltage interfacing circuit employs protection circuits and novel n-well biasing of MOS transistors. To drive the high voltage environment at the high voltage swing, the voltage interfacing circuit employs a bias generator circuit to bias buffer transistors supplied with the high voltage. As example applications, the voltage interfacing buffer enables a 3 volt or 3.3 volt integrated circuit chip to drive TTL as well as CMOS voltage levels. Moreover, the voltage interfacing buffer enables a 2 volt integrated circuit chip to drive TTL voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.