Circuitry for minimizing peak power in an amplifier carrying a plurality of signals of differing frequencies
US5300894A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1992 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Oct 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/34
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In plural channel amplifier systems processing many phase locked signals of different frequencies as a combined signal, these signals may drift into a phase convergence causing a peak power occurrence in the amplifier which greatly exceeds the rated capacity of the amplifier system. Therefore, in accord with the invention, a dynamic adjustment system is provided to minimize the peak power to which the amplifier is subjected by adjusting the relative phase relationships of the many signals. The dynamic adjustment system includes a peak power detector, a hard wired logic decision circuit and a timing control to control phase shift adjustment steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.