Electrostatic discharge protection for CMOS integrated circuits

US5301084A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventor

• William E. Miller · Los Gatos, US

Key dates

• Filing date: Aug 21, 1991
• Grant date: Apr 5, 1994
• Expiry date: Aug 21, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/711

Abstract

An electrostatic discharge ("ESD") protection circuit for use in CMOS I.C. devices provides a low voltage path to and from each input and output ("I/O") pad and power pad by using the wide, low resistance metal VCC and Vss rings and parasitic bipolar transistors configured as three terminal devices at each I/O and power pad. The present invention also provides a clamp, between the VCC and VSS rings, capable of being rapidly switched into the conducting state during an ESD event so as to shunt excess bias current that could otherwise damage reverse biased junctions during an ESD event.