Memory selection/deselection circuitry having a wordline discharge circuit
US5301163A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1992 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Feb 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selection circuit for a bipolar ECL memory having memory cell connected to cell selection lines and, more particularly, to upper and lower wordlines. The circuit includes a line driver connected to the upper wordline, an input stage for controlling the line driver to activate the upper wordline connected thereto in response to an address signal, and a switching device responsive to the input stage for applying a discharging current to the lower word line to speed up deactivation of the memory cell in response to a change in the address signal. In one embodiment, the line driver is also turned on at an increased rate for a limited time following application of the address signal to speed up the activation of the line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.